(1) Field of the Invention
The invention relates to a method of forming shallow trench isolation in the fabrication of integrated circuits, and more particularly, to a method of forming planarized shallow trench isolation in the fabrication of integrated circuits.
(2) Description of the Prior Art
Shallow trench isolation (STI) is desirable for improved planarity over other isolation techniques. Chemical-mechanical polishing (CMP) processes are key to forming STI regions. However, a reverse mask is often needed to form STI due to low CMP selectivity for oxide to nitride and the dishing effect at wide field regions. Therefore, to overcome these problems, a slurry having a high selectivity of oxide to nitride and high planarity is needed. Furthermore, a high selectivity CMP process can induce macro or micro-scratches. Thus, reducing scratches is also an important topic. Another issue for STI CMP is pattern density effect. This will result in a large variation in trench oxide thickness after CMP which leads to difficulties in controlling polysilicon photolithography and etching. It is desired to find a process to resolve all of these critical issues.
U.S. Pat. No. 6,043,133 to Jang et al shows a CMP STI process with reverse mask. U.S. Pat. No. 6,107,159 to Chuang, U.S. Pat. No. 5,837,612 to Ajuria, U.S. Pat. No. 5,950,093 to Wei, and U.S. Pat. No. 5,889,335 to Kuroi et al show other STI processes.